The invention relates to a pattern inspection apparatus of a substrate having a fine circuit pattern like a semiconductor device, liquid crystal, or the like and, more particularly, to a pattern inspection apparatus which is suitable when it is applied to a pattern inspection on a wafer during a semiconductor device manufacturing step.
An inspection of a semiconductor wafer will be described as an example. A semiconductor device is manufactured by repeating a step of transferring a pattern formed on a photomask onto the semiconductor wafer by a lithography process and an etching process. In the manufacturing step of the semiconductor device, whether or not the lithography process, the etching process, and the like have correctly been executed, occurrence of a foreign matter, or the like largely influences on a yield of the semiconductor device. Therefore, a method of inspecting the pattern on the semiconductor wafer in order to early or preliminarily detect an abnormality or occurrence of a defect has been executed hitherto.
As a method of inspecting the defect existing in the pattern on the semiconductor wafer, a defect inspection apparatus in which white light is irradiated onto the semiconductor wafer and the same kinds of circuit patterns of a plurality of LSIs are compared by using an optical image has been put into practical use. An outline of the inspection system has been disclosed in “Monthly Semiconductor World”, pages 96-99, August, 1995. According to the inspecting method using the optical image, there have been disclosed: a system in which an area on a substrate which has been optically illuminated is formed as an image by a time delay integration sensor and the image is compared with design characteristics which have previously been inputted, thereby detecting the defect as disclosed in JP-A-3-167456; and a method whereby image deterioration at the time of obtaining an image is monitored and it is corrected upon detection of the image, thereby performing comparison inspection in a stable optical image as shown in JP-B-6-58220. In the case where the semiconductor wafer in the manufacturing step is inspected by such optical inspection systems as mentioned above, a residual or a defect of the pattern having a silicon oxide film or a photosensitive photoresist material through which light is transmitted on the surface cannot be detected. An etching residual or non-opening defect of a micro conductive hole which is equal to or smaller than resolution of an optical system cannot be detected either. Further, a defect occurring in a stairway bottom portion of a wiring pattern cannot be detected.
As mentioned above, since the defect detection by the optical image becomes difficult due to fine patterning of the circuit pattern, complication of the circuit pattern shape, and variation of the material, a method of comparison inspecting the circuit pattern by using an electron beam image whose resolution is higher than that of the optical image has been proposed. In the case of comparison inspecting the circuit pattern by the electron beam image, it is necessary to obtain the image at a very high speed as compared with that in the observation by a scanning electron microscopy (hereinafter, abbreviated to SEM) in order to obtain a practical inspecting time. It is necessary to assure the resolution of the image obtained at the high speed and an S/N ratio of the image.
As a comparison inspection apparatus of the pattern using the electron beam, in J. Vac. Sci. Tech. B, Vol. 9, No. 6, pp. 3005-3009 (1991), J. Vac. Sci. Tech. B, Vol. 10, No. 6, pp. 2804-2808 (1992), JP-A-5-258703, and U.S. Pat. No. 5,502,306, there has been disclosed a method whereby an electron beam having an electron beam current which is 100 or more times (10 nA or more) as large as that of the ordinary SEM is irradiated onto a conductive substrate (X-ray mask or the like), one of a secondary electron, a reflection electron, and a transmission electron which are generated is detected, and an image formed from its signal is comparison inspected, thereby automatically detecting a defect.
As a method of inspecting or observing a circuit substrate having an insulating material by an electron beam, in JP-A-59-155941 and in “Electron, Ion Beam Handbook”, (The Nikkan Kogyo Shimbun Ltd.), pages 622-623, there has been disclosed a method of obtaining a stable image by irradiating a low-acceleration electron beam of 2 keV or less in order to reduce an influence of charging. Further, a method of irradiating ions from the back surface of a semiconductor substrate has been disclosed in JP-A-2-15546. A method of setting off charging to an insulating material by irradiating light onto the surface of a semiconductor substrate has been disclosed in JP-A-6-338280.
In the case of the electron beam of a large current and low acceleration, it is difficult to obtain an image of high resolution due to a space-charge effect. As a method of solving such a problem, however, a method whereby a high-acceleration electron beam is decelerated just before a sample and irradiated substantially as a low-acceleration electron beam on the sample has been disclosed in JP-A-5-258703.
As a method of obtaining an electron beam image at a high speed, a method of obtaining such an image by continuously irradiating an electron beam onto a semiconductor wafer on a sample stage while continuously moving the sample stage has been disclosed in JP-A-59-160948 and JP-A-5-258703. As a detection apparatus of a secondary electron which has been used in the conventional SEM, a construction by a scintillator (Al-deposited phosphor), a light guide, and a photomultiplier has been used. However, in such a type of detection apparatus, since the light emission by phosphor is detected, frequency response characteristics are bad and it is improper to form the electron beam image at a high speed. To solve such a problem, as a detection apparatus for detecting a secondary electron signal of a high frequency, detecting means using a semiconductor detector has been disclosed in JP-A-5-258703.
For inspection of an external appearance of a repetitive pattern represented by a semiconductor wafer, there has been known a comparison system in which an external appearance of an object to be inspected (hereinafter, referred to as an inspection object) is photographed, a reference image serving as a reference of the inspection is compared with image data of an inspection image serving as an inspection target and, if there is a difference between the compared data, such a case is extracted as a defect. In the case of such a comparison system, it is presumed as a prerequisite that the reference image and the inspection image are the same pattern. Such a method is effective to the inspection target in which the same circuit pattern has repetitively formed like a semiconductor wafer. As a reference image, there is a case where design information or a real pattern which is adjacent or close to the inspection image is used. If the inspection object is the semiconductor wafer, a number of chips (1 device) having the same circuit pattern are arranged on one wafer. A method of respectively comparing photographed images of those chips as reference images and inspection images is called a die comparison. A method of respectively comparing photographed images of the patterns repetitively arranged in the same chip as reference images and inspection images is called a cell comparison. As an example of such comparison inspection using the images, a technique disclosed in JP-A-9-89794 has been known.
In association with the realization of high functions of a semiconductor, a wafer in which a plurality of cell mat areas exist on one chip and, since design rules in the cell mat areas differ, cell pitch intervals for the comparison inspection differ has appeared. Further, in association with the production of a small quantity and many kinds, it is demanded to shorten a recipe forming time and an inspecting time. In the conventional inspection apparatus, processes in which the cell pitch of each cell area is measured/calculated, the inspection is made every cell area, and thereafter, inspection results of the respective cell areas which are obtained from them are integrated as one inspection result are executed. An ease of use is bad in both of management and creation of the recipe. Further, since a plurality of inspection steps are executed every cell, there is such a drawback that the inspecting time becomes long.
In the case of any of the cell comparison and the die comparison, as for the image data which is transferred to a defect analyzing unit, the reference image and the inspection image need to be transferred as a pair. In the case of the die comparison, the image which is one-chip precedent to the inspection image is generally used as a reference image. However, for example, if a defect is detected in the first chip shown in FIG. 16A, since the one-chip precedent image does not exist and there is no reference image, defect analysis of the first chip is impossible. Further, if a defect is detected in the (n+1)th chip in a wafer edge portion as shown in FIG. 16A, the data of the nth chip which is one-chip precedent exists as image data. However, in the case of the external appearance inspection of the semiconductor wafer, in the reference image for the inspection image, the farther a distance is physically away, the more the peripheral conditions upon obtaining the images are different. Therefore, the reference image includes a larger amount of positional deviation error and a larger amount of error of image concentration or the like and cannot be used as a reference image. Therefore, even if the defect is detected in the (n+1)th chip in the wafer edge portion, the defect analysis is impossible.
Likewise, in the die comparison, in the case of executing such an operation that a scan on the wafer is turned back at the edge of the wafer and the image is repetitively photographed as shown in FIG. 16B, when a defect is detected in the (n+1)th chip and the image is compared with that of the nth chip, if such a case is compared with the relation between the (n+1)th chip and the nth chip in the case of FIG. 16A, the physical positions are close. However, since columns of the (n+1)th chip and the nth chip of the chip layouts are different in FIG. 16B, when compared with the relation between the adjacent chips of the same column (for example, the nth chip and the (n−1)th chip), the conditions upon obtaining the images are different and the reference image includes a larger amount of positional deviation error and the like. Although there is no problem if such an error lies within a correction range of an image processing function, if not, even in the case of FIG. 16B, there is also a possibility that the image of the nth chip cannot be used as a reference image of the (n+1)th chip.
As mentioned above, if the defect is detected in the chip in the semiconductor wafer edge portion and becomes a defect analysis target, since the one-chip precedent image does not exist, the reference image does not exist and a situation that the defect analysis cannot be performed occurs.
In the cell comparison, if a defect is detected in each of circuit patterns having different cell pitch areas such as cell pitch A area 1503 and cell pitch B area 1504 mounted in one chip as shown in FIG. 15, image data for analyzing the defect detected in the cell pitch A area needs image data at a position where the reference image is away from the inspection image by a distance corresponding to a cell pitch A, and image data for analyzing the defect detected in the cell pitch B area needs image data at a position where the reference image is away from the inspection image by a distance corresponding to a cell pitch B. That is, in the case of the cell comparison, the position of the reference image for the inspection image differs depending on the cell pitch area where the defect has been detected. However, hitherto, a plurality of cell pitches in the case of the cell comparison cannot be designated. Therefore, the inspection of the cell pitch A area and the inspection of the cell pitch B area cannot be simultaneously performed. The inspection of the areas of the different cell pitches is performed in accordance with a flow shown in FIG. 17.
In FIG. 17, first, the cell pitch of the inspection area is set (S1701) and an image photographed by a sensor is stored into an image memory 1105 (S1702). Subsequently, an extracting position of the inspection image and reference image position information are set (S1703). The inspection image and the reference image are extracted from the image memory 1105 on the basis of those position information and transferred to a defect analyzing unit 1108 (S1704). Since only one cell pitch is set in S1701, information showing whether or not the inspection of the areas of the different cell pitches is necessary is inputted (S1705). If it is necessary, the processing routine is returned to S1701 and the above processing loop is repeated. As mentioned above, according to the related art, since it is necessary to set the cell pitch for each cell pitch area and execute the inspection again, efficiency is very low.
Further, in the die comparison and the cell comparison, since definitions of the reference images which are necessary for the inspection images are different, the cell comparison and the die comparison cannot be mixedly executed.
In association with the realization of high functions of a semiconductor, a wafer in which a plurality of memory cell areas of different design rules exist on one chip has appeared. Further, in association with the production of a small quantity and many kinds, it is demanded to shorten the recipe forming time and the inspecting time. If the design rules differ, in addition to the existence of the plurality of cell mat areas as mentioned above, degrees of fineness and coarseness of the memory cell patterns are different, so that brightness values of the detected images differ. Therefore, it is necessary to change an inspection threshold value every memory cell area. In the conventional inspection apparatus, processes in which the inspection threshold value is changed every memory cell area, the inspection is repetitively executed, and thereafter, inspection results of the respective memory cell areas which are obtained are integrated as one inspection result are executed. There is such a drawback that the inspecting time becomes long because a plurality of inspecting steps are repeated. Further, since a plurality of recipes are needed for one inspection, ease of use is bad in both of the management of the inspection recipes and the creation of the recipes.